Samsung Introducing Backside Power Supply Technology To Its 2nm Process In 2025, Will Reduce Chip Area By 19%, Efficiency Improvements Inbound

Samsung may not have much success with its 3nm GAA process, but it intends to make amends with its next-generation 2nm technology, which is said to enter mass production next year. To gain an edge against its foundry rival TSMC, a new report states that the Korean giant is introducing Backside Power Supply (BSPDN) technology, which aims to offer several benefits, which we will discuss here.

BSPDN technology was supposedly tested with two ARM cores, and Samsung managed to reduce the chip area of both by a varying degree

It is going to be a competitive matchup between Samsung and TSMC as both aim to introduce the best version of their 2nm nodes. For Samsung, a report from Chosun states that Backside Power Supply technology is expected to be a game-changer and that the initial test results have exceeded the company’s target. As for the specific testing, Samsung was said to have applied this technology to two unnamed ARM cores, with the chip area reduced by 10 percent and 19 percent.

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With the chip area reduced, Samsung can effectively start mass producing SoC designs that tout a smaller surface area, and not just that, the earlier tests carried out helped succeed in improving performance and power efficiency levels considerably. As the report states, BSPDN is a new process that is yet to be commercialized, though it is not mentioned if this was due to cost constraints or if there was not much thought given towards exploring this technology.

In any case, as the name suggests, Backside Power Supply are power lines placed at the back of the wafer, which separates the circuit and power supply space. This helps to maximize efficiency, and an opportunity also exists to improve semiconductor performance. Currently, the power lines are placed at the top of wafers since that is where the circuit is drawn and creates a ton of convenience for the manufacturer.