Peeking under the hood of AMD's Zen 5: Here's what has been changed and improved in the new CPU architecture

It's not hyperbole to say that Zen saved AMD. The fully redesigned CPU architecture, first launched in 2017, swept away all the company's past mistakes and along with chiplets, Infinity Fabric, and 3D V-cache, it paved the way to profitability and market-leading performance. There have been some big steps forward in the chip design since then but with the freshly announced Zen 5 at Computex 2024, AMD isn't doing anything majorly different—just a collection of small changes that combine to give some notable performance boosts, in the right applications.

Let's start with what hasn't changed. Zen 5 is fundamentally the same as Zen 4, with the CCDs (Core Complex Dies) comprising up to eight cores, sharing 32MB of L3 cache. The IOD (Input/Output Die) is practically the same, too, although few details about its feature set have been released so far.

So, you're not getting any more cores, threads, or cache in Zen 5 compared to Zen 4. That may disappoint some folks but given that there was little to complain about the previous architecture, there wasn't much call for any sweeping changes to be implemented.

What is new, though, lies deep within the core structures themselves and it mostly revolves around getting more data to where it needs to be, while improving the overall efficiency of a CCD's number-crunching ability. The Zen 5 announcement is quite light on specifics, but here's what we've been told.

Each core's branch prediction unit has been tweaked to make it more accurate and spit out results quicker. This circuit is responsible for determining what instructions are most likely to be next in line for a core to process, and the rest of the core then fetches the necessary data and instructions from caches based on what the predictor calculates. If it gets it wrong, then precious cycles are wasted in getting the right information.

Thus a branch predictor that's more accurate and responds faster means the overall efficiency of the processing side of the chip is better,