AMD To Provide Patch That Improves Ryzen 9000 “Zen 5” Inter-Core & Chiplet Latency

AMD is reportedly working on a new BIOS patch that will help improve inter-core latency on Ryzen 9000 "Zen 5" Desktop CPUs.

AMD's Ryzen 9000 "Zen 5" CPUs To See Further Improvements As Red Team Plans To Roll Out BIOS Patch To Improve Inter-Core Latencies

AMD's Zen 5-based Ryzen 9000 Desktop CPUs didn't provide the performance uplift we all expected. Even though one of the reasons for this can be attributed to the poor optimizations for Windows 11, it's not the only reason. The unoptimized Core Parking is one of the culprits resulting in slower performance than ideal, supposedly due to the unfinished software and BIOS support.

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In Anandtech's review of the Ryzen 9 9950X, it was found that the Zen 5 CPU had significantly higher inter-CCD latency compared to its predecessor. This is despite both Zen 4 and Zen 5 CPUs sharing a similar I/O die & infinity fabric design. However, a recent report by Geekerwan at Bilibili (via @9950pro) suggests that AMD is working to address this issue through a future BIOS patch.

The inter-CCD latency is how quickly the data or instructions are transferred between the two Zen 5 CCDs (Core Complex Dies) within the Ryzen 9000 CPUs. This fabric is used for communication with multiple chiplets such as CCDs and IODs. As the Ryzen 9 9950X & Ryzen 9 9900X contain two CCDs, with each CCD carrying 8 Zen 5 cores, the programs that utilize more than 8 cores need to have the data transferred between the CCDs for faster execution.

Unfortunately, unlike its predecessor Ryzen 9 7950X, the AMD Ryzen 9 9950X has almost twice the CCD to CCD latency compared to the former. The average inter-CCD latency for Zen 5 averages at 180ns compared to 76ns on the 7950X. This results in slower data transfer between the CCDs, resulting in slower multi-threaded performance in some workloads than expected.

The higher inter-CCD latency is not